The present invention relates to noise-shaping digital amplifiers, and specifically to techniques for generating a sampling clock for such amplifiers. It should be noted at the outset that although the invention is described herein with reference to a band pass (e.g., RF) implementation, the present invention is also applicable to other amplifier configurations such as, for example, base band audio amplifiers or motor drive circuits.
FIG. 1 shows an RF bandpass noise-shaping amplifier 100 designed according to techniques described in U.S. Pat. No. 5,777,512 for METHOD AND APPARATUS FOR OVERSAMPLED, NOISE-SHAPING, MIXED-SIGNAL PROCESSING issued Jul. 7, 1998, the entire disclosure of which is incorporated herein by reference for all purposes. RF amplifier 100 includes a frequency selective network 102 which, using continuous-time feedback, noise shapes the modulated RF input. Network 102 comprises at least one resonator stage having a transfer function designed to pass a band centered around, for example, 900 MHz.
A/D converter 104 converts the noise shaped RF signal to digital data using a sampling frequency fs which, in this example, is 3.6 GHz. A/D converter 104 may comprise a single comparator. Alternatively, A/D converter 104 may comprise two comparators configured to implement three-level switching as described in copending U.S. patent application Ser. No. 09/796,845 for DUAL INDEPENDENTLY CLOCKED ANALOG-TO-DIGITAL CONVERSION FOR A DIGITAL POWER AMPLIFIER filed simultaneously herewith, the entire disclosure of which is incorporated herein by reference for all purposes.
Gate drive circuitry 106 takes the pulse train from A/D converter 104 and generates gate drive for each of FETs 108 and 110 of the power output stage of amplifier 100. The output power stage shown includes three inductors L1, L2 and L3, and capacitor C1. This configuration creates two separate resonances at nodes A and B respectively when the corresponding one of FETs 108 and 110 is off.
The continuous-time feedback to frequency selective network 102 is provided via feedback path 112. The output signal of the power stage is passed to a matching network 114 which passes the output RF signal to antenna 116 for transmission.
Using a fixed clock to generate the clock for A/D converter 104 (i.e., fs) has its drawbacks. First, it is generally desirable for the timing of the resonances at nodes A and B to match the timing of this clock to maximize efficiency. However, in reality, the resonances at nodes A and B tend to move around in frequency due, for example, to reflections from matching network 114 and process variations. Second, because of design complexity, it is generally undesirable to require a separate clock for the A/D converter in such a design.
It is therefore desirable to provide a sampling clock for the A/D converters in integrated circuit amplifiers which tracks output stage resonance oscillations yet does not add unduly to circuit complexity.
According to the present invention, one or more of the resonances in the output switching stage of an amplifier design are used to generate the clock signal(s) for the amplifier""s A/D converter(s). According to one embodiment, where the output stage comprises two switching devices, the resonance nodes associated with the two devices are alternately used to generate the clocks signal(s).
Thus the present invention provides an electronic device including sampling circuitry and at least one switching device. Each switching device has resonance circuitry associated with the output terminal thereof. The resonance circuitry and the at least one switching device have at least one resonance oscillation associated therewith. The electronic device further comprises clock generation circuitry which generates a clock signal for the sampling circuitry at least in part from the at least one resonance oscillation.
A further understanding of the nature and advantages of the present invention may be realized by reference to the remaining portions of the specification and the drawings.